1. Field of the Invention
The present invention relates to a semiconductor device and, particularly, to an element isolation region of a semiconductor device, which is composed of a LOCOS type field oxide film and a U-trench isolation region.
2. Description of the Prior Art
The LSI of semiconductor device on a silicon substrate has been realized by providing element isolation regions each between adjacent ones of a plurality of transistors. Such element isolation region to be used in a semiconductor device includes P-N junction isolation region, field oxide film such as LOCOS field oxide film and U-trench isolation region, etc. The P-N junction isolation region and the U-trench isolation region are isolation regions for elements having such deep P-N junction as in a collector region of a bipolar transistor. On the other hand, the field oxide film provides an isolation region for elements having shallow P-N junction such as between an element formed on a silicon substrate surface and a wiring formed on the substrate or between a source-drain region of a MOS transistor.
Thus, for the element isolation region of a semiconductor device comprising MOS transistor, the field oxide film is used and, for the element isolation of semiconductor device comprising bipolar transistor, combination of the P-N junction or U-trench isolation and the field oxide film. With decrease of element size, the LOCOS type field oxide film and the combination of the LOCOS type field oxide film and the U-trench isolation region is used mainly for a semiconductor device comprising MOS transistor and for a semiconductor device comprising bipolar transistor, respectively, in views of self-alignment and reduction of element isolation region.
In a semiconductor device including a MOS transistor, the MOS transistor was a P channel MOS transistor, firstly, and, then, an N channel MOS transistor was used and, currently, a MOS transistor is used mainly. The semiconductor device using a CMOS transistor employed initially an N well or a P well and now employs an N well and a P well. Therefore, in the semiconductor device including MOS transistor, an element isolation region for isolating the N well from the P well, both having deep P-N junctions, is necessary and, further, for latch-up problem, the use of a U-trench isolation region is becoming considered. Further, in view of a BICMOS transistor composed of a CMOS transistor and a bipolar transistor which is becoming popular, the necessity of element isolation region including a LOCOS type field oxide film and a U-trench isolation region is increasing.
Now, a conventional element isolation region including a LOCOS type field oxide film and a U-trench isolation region will be described. Such element isolation region comprises a field oxide film formed on a silicon substrate surface by a LOCOS process, a U-trench penetrating the field oxide film into the silicon substrate, a channel stopper provided on a surface portion of the silicon substrate which is a bottom face of the U-trench, an insulating film covering a surface of the silicon substrate portion constituting a wall of the U-trench, a filler in the U-trench and an insulating film filling the U-trench up to an upper end of the U-trench. The filler is usually of a polysilicon film. In this structure, the insulating film burying the U-trench to close the upper end thereof is formed by thermal oxidation of this polysilicon film which is connected to the field oxide film. With the connection of these oxide films, a surface flatness of the element isolation region is maintained to some extent which will be described later. The insulating film covering the wall of the U-trench comprise a silicon oxide film obtained by, for example, oxidizing a surface of silicon substrate. The channel stopper is formed by impurity ion injection of the same conductivity type as that of the silicon substrate to the bottom face of the U-trench, after the latter is formed by etching.
There are two typical methods for fabrication of such element isolation region. These methods will be described by taking an element isolation region for a NPN bipolar transistor as an example.
The first method comprises the following steps: An N.sup.+ buried layer is formed in a surface of a P type silicon substrate and an N type epitaxial layer is formed on the P type silicon substrate surface including an N.sup.+ type buried layer. A field oxide film of LOCOS type is formed on a surface of the epitaxial layer. Then, a U-trench penetrating the field oxide film, the N.sup.+ type epitaxial layer and the N type buried layer is formed by etching. A silicon oxide film covering portions of the N type epitaxial layer and the N.sup.+ type buried layer and a surface portion of the P type silicon substrate exposed on a wall of the U-trench is formed by thermal oxidation. A P type channel stopper is formed on a surface portion of the P type silicon substrate exposed on a surface portion of the P type silicon substrate exposed on a bottom face of the U-trench, by ion-injection of boron. On the whole surface of this wafer, a non-doped polysilicon film is deposited by a CVD process. The polysilicon film is etched back, leaving a portion thereof within the U-trench. On a top face of the polysilicon film, a silicon oxide film is formed by thermal oxidation by which the upper end of the U-trench is closed.
According to the second method, an N.sup.+ type buried layer is formed in a surface of a P type silicon substrate and, then, an N type epitaxial layer is formed on the surface of the P type silicon substrate including the N.sup.+ type buried layer. A silicon oxide film is formed on a surface of the N type epitaxial layer by a CVD process. Portions of the silicon oxide film on a region in which a U-trench is to be formed are removed. With using the silicon oxide film as an etch mask, the N type epitacial layer, the N.sup.+ type buried layer and the P type silicon substrate are etched in the order, resulting in a U-trench. A P type channel stopper is formed on the P type silicon substrate exposed on a bottom face of the U-trench by ion injection of boron. The silicon oxide film used as the mask in the etching step is removed. A silicon oxide film is formed on the N.sup.+ type buried layer, the P type silicon substrate and the N type epitaxial layer which are exposed on the wall of the U-trench, by thermal oxidation. On the whole surface, a non-doped polysilicon film is deposited by a CVD process. The polysilicon film is etched back, leaving a portion thereof within the U-trench. On the whole surface, a pad oxide film and a silicon nitride film are formed. A portion of the silicon nitride film on an area in which a field oxide film is to be formed is removed. The field oxide film is formed on the N type epitaxial layer by a LOCOS process, and a silicon oxide film is formed on an upper end of the U-trench by thermal oxidation of the polysilicon film surface. The remaining silicon nitride film and the pad oxide film are removed.
In the first method, the top face of the silicon oxide film formed by thermal oxidation of the polysilicon film buring the U-trench and closing the upper end of the U-trench, hardly becomes coplanar with the top face of the field oxide film, resulting in a step at a joining portion therebetween. In the second method, a recess is formed at a junction between the silicon oxide film closing the upper end of the U-trench and the field oxide film. That is, in these methods, it is difficult to obtain a complete flatness at the junction of these oxide films. In this case, breakage of a wiring formed on the junction area tends to occur.
In order to solve these problems, a third method has been proposed by y.-C. Simon Yu, et al. on J. Elecytochem. Soc., Vol. 137, No. 6, pp 1942-1950, (1990). According to this proposal, the LOCOS field oxide film is formed in two steps. First, a first field oxide film is formed on a top face of the polysilicon film burying the U-trench. Then, a second field oxide film is formed in an area adjacent to the first field oxide film.
In detail, in the third method, an N.sup.+ buried layer is formed on a P type silicon substrate and an N type epitaxial layer is formed on the P type silicon substrate surface including the N.sup.+ type buried layer. A pad oxide film and a silicon nitride film are formed on a surface of the N type epitaxial layer. Portions of the silicon nitride film and the pad oxide film on an area in which the U-trench is to be formed are removed by etching and, then, the N type epitaxial layer, the N.sup.+ type buried layer and the P type silicon substrate in the same area are etched in sequence, resulting in the U-trench. In this series of etching steps, the pad oxide film is under cut. A channel stopper is formed on a surface of the P type silicon substrate exposed on bottom face of the U-trench by ion injection of boron. A silicon oxide film is formed on the surfaces of the N type epitaxial layer, the N.sup.+ type buried layer and the P type silicon substrate exposed on a wall of the U-trench by thermal oxidation. This silicon oxide film is connected to the pad oxide film in the vicinity of the upper end of the U-trench. On the whole surface, a non-doped polysilicon film is deposited by a CVD process. The polysilicon film is etched back such that the portion thereof within the U-trench is left as it is. The first field oxide film is formed on the surface of the polysilicon film by a LOCOS process using the silicon nitride film as a mask. A portion of the silicon nitride film on an area in which the second field oxide film is to be formed is removed by etching and, then, by using a LOCOS process again, the second field oxide film connected to the first film oxide film is formed on the N type epitaxial layer. In the junction between the first and second field oxide films, there is no step or recess formed. Therefore, it is possible to obtain a substantially complete flatness in the junction area.
In the conventional element isolation region including the LOCOS type field oxide film and the U-trench isolation region which is buried with the polysilicon film, the flatness of the surface of element isolation region including the junction area of these two isolation regions is maintained. However, there is a problem in the U-trench isolation region which is buried with the polysilicon film, regardless of the the structure and formation of the field insulating film. That is, the problem resides in the formation of the silicon oxide film on the upper end of the U-trench by the thermal oxidation of the top face of the polysilicon film burying the U-trench. In the thermal oxidation, the polysilicon film expands in volume with expansion coefficient of about 1.5 times that of the surrounding silicon, so that stress is exerted on silicon crystal surrounding the polysilicon film and crystal defects may be formed, resulting in leakage current. Further, parasitic capacitance between regions adjacent to each other through the U-trench is not reduced by the presence of the polysilicon film burying the U-trench. The parasitic capacitance may be increased if the polysilicon film which is non-doped, is doped with conductive impurity.
N. Sugiyama et al. propose in 1989 Symposium on VLSI Technology Digest papers, pp 59-60, a method for solving the problem caused by the volume expansion of polysilicon in a U-trench isolation region. In this article, a LOCOS type field oxide film is not used, and, instead thereof, a field insulating film is formed on a silicon substrate surface by a CVD process after a U-trench is formed. The U-trench is buried with a BPSG film. A bipolar transistor is formed by using the U-trench isolation region filled with the BPSG film and an emitter-collector leakage current was measured. A result showed a substantial improvement of leakage current, compared with a bipolar transistor with the U-trench isolation region filled with a polysilicon film.
The formation of the U-trench isolation region buried with BPSG film is summarized as below: A U-trench is formed in a predetermined portion of a silicon substrate by etching the portion. On a silicon surface including the silicon substrate exposed on a wall of the U-trench is thermally oxidized to form a silicon oxide film. A silicon nitride film is deposited thereon. A BPSG film is deposited thereon by a CVD process and a surface of the BPSG film is flattened by heat treatment. The BPSG film is etched back to make a top face thereof and an upper end of the U-trench coplanar. The purpose of the silicon oxide film is to obtain a good contact of the silicon nitride film and the purpose of the silicon nitride film is to protect the silicon substrate against the etch back of the BPSG film. Further the silicon oxide film and the silicon nitride film serve to prevent diffusion of boron and phosphor from the BPSG film to the silicon substrate during the heat-treatment of the BPSG film. This formation utilizes the thermal reflow characteristics of the BPSG film.
The element isolation of proposed by M. Sugiyama et al. is not advantageous in reducing the size of semiconductor element. For example, when a bipolar transistor is formed, it is necessary to separately form a hole of a field insulating film for forming a collector plug region and holes of the field oxide film for forming an emitter region and a base region. This means that it is impossible to use a self-alignment scheme. Thus, the number of photolithographic steps is increased and the alignment margin of photo masks is increased. These problems become severe when a semiconductor includes MOS transistor.
It is not practical to merely combine a U-trench isolation region according to Sugiyama et al, and a LOCOS field oxide film. That is, when such combination is used, a pad oxide film and a silicon nitride film are formed on a surface of a silicon substrate. Then, a portion of the silicon nitride film on an area of the substrate surface in which a field oxide film is to be formed is etched away. After the field oxide film is formed thereon by a LOCOS process, portions of the field oxide film and the silicon substrate in an area in which a U-trench is to be formed are etched away, resulting a U-trench. Then, a silicon oxide film is formed on a portion of the silicon substrate exposed on the wall of the U-trench by thermal oxidation and, thereafter, a BPSG film is deposited on the whole surface by a CVD process and its surface is flattened by the heat treatment. Then, the BPSG film is etched back to make a top face of the BPSG film substantially coplanar with an upper end of the U-trench, leaving the BPSG film on the pad oxide film. In order to completely remove the BPSG film on the pad oxide film by etch back thereof, the top face of the BPSG film becomes lower than the upper end of the U-trench. As such, even if an insulating film covering the top face of the BPSG film is formed, there is a step between the field oxide film and the BPSG film, causing a wiring passing over the U-trench isolation region to be easily broken.